Semiconductor flash device

ABSTRACT

A flash memory device includes a floating gate made of a multi-layered structure. The floating gate includes a hetero-pn junction which serves as a quantum well to store charge in the floating gate, thus increasing the efficiency of the device, allowing the device to be operable using lower voltages and increasing the miniaturization of the device. The floating gate may be used in n-type and p-type devices, including n-type and p-type fin-FET devices. The stored charge may be electrons or holes.

FIELD OF THE INVENTION

The present invention relates most generally to semiconductor devicesand more particularly to floating gate charge storage devices such astransistors.

BACKGROUND

Floating gate transistors are widely used in semiconductor manufacturingbecause of their ability to store charge in the floating gate disposedbetween lower and upper dielectrics formed beneath the gate electrode.Floating gate transistors are used to form flash memory cell structuressuch as discussed in K. Kim and G. Koh, “Future Memory TechnologyIncluding Emerging New Memories”, Intl. Conf. on Microelectronics, p.377-384, 2004, and G. Atwood, “Future Directions and Challenges forETox™ Flash Memory Scaling”, IEEE Trans. Device and MaterialsReliability vol. 4, no. 3, September 2004. Such cell structurestypically use a dual-poly floating gate structure with the polysiliconfloating gate serving as a charge storage medium as shown in FIGS.1A-1C. The tunnel-oxide of such devices is usually 90 angstroms—110angstroms and the inter-poly or upper dielectric is usually a compositeof ONO (Oxide-Nitride-Oxide) with an equivalent oxide thickness of about200 angstroms to about 300 angstroms, roughly 2× or 3× the tunnel-oxidethickness. The thickness of the tunnel-oxide and upper dielectric aredetermined by the stringent retention requirements of retaining chargefor greater than ten years at 125° C.

Programming of the floating gate flash memory cells is typicallyperformed by channel hot electron (CHE) injection or channel F-N(Fowler-Nordheim) tunneling. Erasure of the cell is typicallyaccomplished by F-N tunneling through the tunnel-oxide and into thechannel. The cell may be an ETox™ cell based on either NMOS or PMOStransistors with floating gate storage of electrons or holesrespectively. The channel current during the read operation is modulatedby the amount of charge stored on the floating gate representing logicstates “1” or “0”. The amount of stored charge is limited by thematerial used for the floating gate which is typically a singlepolysilicon layer.

FIGS. 1A-1C illustrate a typical conventional floating gate transistor100 that includes gate structure 102 formed over channel 104 formed in asubstrate. Channel 104 is between source and drain regions 108. Gatestructure 102 includes lower tunnel-oxide 110 and upper dielectric 112,described above, along with floating gate 114 and gate electrode 116. Insuch conventional floating gate transistors, each of gate electrode 116and floating gate 114 are formed of a single layer of polycrystallinesilicon. The exemplary floating gate transistor may be an ETox™ cellthat includes p-well 122, n-well 124 and p-type substrate 126. FIGS.1A-1C illustrate the exemplary floating gate transistor 100 in read,program, and erase operations, respectively. Charge is indicated byelectrons 130.

The conventional technology is limited by the ability of the floatingpolysilicon gate to store charge. The minimum thickness of thetunnel-oxide in upper dielectrics is determined by the stringentrequirement of charge retention for greater than ten years at 125° C.Once the thickness of these dielectric materials is determined, the cellsize is then set by the required coupling ratio (typically about 0.8).Often the floating gate cell would benefit from increased area toaccommodate larger capacitance coupling between the floating gatepolysilicon and the control gate. An increase in device area isobviously is quite undesirable as the drive to increase integrationlevels mandates increasingly smaller features of smaller area.

As such, there is a need for better charge retention which will enableboth the tunnel-oxide and the upper dielectric to be further scaled downwithout a trade-off to the retention performance or requiring anincrease in size/area. Improved charge retention would enable thedesirable result of further scaling down the cell size and also reducingthe program/erase operating voltage accordingly. The present inventionaddresses these shortcomings and provides a floating gate with superiorcharge retention characteristics.

SUMMARY OF THE INVENTION

To address these and other objects, and in view of its purposes, thepresent invention provides a floating gate transistor comprising a lowertunnel-oxide formed over a substrate, an upper dielectric formed overthe tunnel-oxide, an electrode formed over the upper dielectric, and ap-n junction formed between the tunnel-oxide and the upper dielectric.

In another aspect, provided is a floating gate transistor comprising alower tunnel-oxide formed over a substrate, an upper dielectric formedover the tunnel-oxide, an electrode formed over the upper dielectric,and a quantum well formed between the tunnel-oxide and the upperdielectric.

BRIEF DESCRIPTION OF THE DRAWING

The present invention is best understood from the following detaileddescription when read in conjunction with the accompanying drawing. Itis emphasized that, according to common practice, the various featuresof the drawing are not necessarily to scale. On the contrary, thedimensions of the various features are arbitrarily expanded or reducedfor clarity. Like numerals denote like features throughout thespecification and drawing.

FIGS. 1A-1C are cross-sectional views showing three different logicstates of a conventional floating gate transistor;

FIGS. 2A and 2B show two exemplary embodiments of gate structures of theinventive floating gate transistor;

FIGS. 3A-3C show energy level diagrams that illustrate electron quantumwells;

FIGS. 4A-4C show energy level diagrams that illustrate hole quantumwells;

FIG. 5A is a cross-sectional view showing an exemplary floating gatetransistor according to the invention.

FIGS. 5B-5D show the exemplary floating gate structure in various logicstates; and

FIG. 6 is a cross-sectional view showing an exemplary floating gatetransistor of the invention applied to a fin-FET.

DETAILED DESCRIPTION

The present invention provides a floating gate transistor which may bean ETox™ or other flash memory cell with a multi-layer floating gatethat includes a quantum well for superior charge retention. A thinhetero-pn junction formed between two semiconductor layers may form thequantum well due to band edge offset. The two layers are formed ofmaterials chosen to have different bandgaps. The quantum well confinescharge therein and the storage of charge in the quantum well is used toidentify the logic state of the device. The thin hetero-pn junction maybe lightly doped with n- and p-type dopants respectively, so that it isfully depleted of mobile carriers. The charge trapped inside the quantumwell and the fully depleted multi-layer structure leads to superiorcharge retention of the cell and provides for further scaling downdimensions of the tunnel-oxide and channel length and enables lowvoltage program/erase operations. For example, as a result of thissuperior retention, the tunnel-oxide and upper dielectric may be thinnerthan in conventional ETox™ cells enabling the coupling capacitancebetween the floating gate and the control gate to be larger whichprovides a desirably high coupling ratio without requiring extracoupling area size. The thinner tunnel-oxide enables the memoryprogram/erase to be operated using a reduced voltage.

In one embodiment, the multi-layer floating gate structure may be abi-level structure and in various embodiments the bi-layer structure maybe Si/SiGe, Si/SiC, III-IV compound structures such as AlGaAs/GaAs,GaP/GaAs, InP/GaAs, AlN/GaAs, II-VI compound structures such asZnSe/ZnTe, ZnS/ZnTe, CdS/CdTe, III-V/II-VI compound structures such asZnSe/GaAs but other multi-layer structures may be used as the floatinggate in other exemplary embodiments.

The multi-layer floating gate structure of the present invention may beapplied to flash memory devices such as E-Tox™ developed by Intel, orother flash memory or other floating gate devices.

FIG. 2A shows an exemplary structure including a bi-layer floating gate.Transistor 1 is formed over substrate 13 which may be a bulk siliconsubstrate or may be silicon formed over an insulating substrate, asilicon-on-insulator (SOI) substrate. Substrate 13 may be p-type orn-type and includes channel 4 formed in substrate 13 along tunnel-oxide9. Hence, transistor 1 may be an n-type or p-type transistor indifferent embodiments. Tunnel-oxide 9 may advantageously be a thermallyformed oxide and includes thickness 19 which may range from 12 to 100angstroms in exemplary embodiments. Bi-layer floating gate 3 includestwo layers: semiconductor layer 5 and semiconductor layer 7. Topdielectric 11 is formed over bi-layer floating gate 3. Top dielectric 11may be any of various state-of-the-art high-k materials such as Al₂O₅,HfSiON, or other suitable materials. Top dielectric 11 includesthickness 20 which may range from 12 to 100 angstroms in exemplaryembodiments. Thicknesses 19 and 20 may be advantageously minimized dueto the charge storage ability of bi-layer floating gate 3, and can beless than 70 and 90 angstroms, respectively. Control gate 15 is formedover top dielectric 11 and may be formed of metals such as W, Al, Co orother suitable metals or it may be formed of metal nitrides such as WN,TiN, or TaN or other suitable metal nitrides. In other exemplaryembodiments, control gate 15 may be formed of silicides such as CoSi,TiSi, NiSi or other suitable silicides. Interface 17 formed betweensemiconductor layer 5 and semiconductor layer 7 represents a p-njunction that may form a quantum well.

The two semiconductor layers 5 and 7 are chosen so that one of thelayers is a p-type layer and the other of the layers is an n-type layerthat combine to form a hetero-pn junction and quantum well at interface17 between the layers. In one embodiment, transistor 1 may be an n-typetransistor with an electron quantum well formed at interface 17; inanother exemplary embodiment, transistor 1 may be an n-type transistorwith a hole quantum well formed at interface 17; and, in anotherexemplary embodiment, transistor 1 may be a p-type transistor with anelectron or hole quantum well formed at interface 17. Semiconductorlayer 5 and semiconductor layer 7 are chosen to have different bandgapsin order to trap charges (electrons or holes) in the quantum well formedat interface 17. Substrate 13 may include variously doped wells such asthe substrate shown in FIGS. 1A-1C.

FIG. 2B shows another exemplary embodiment in which multi-layer floatinggate 21 is formed of three layers: upper layer 23, middle layer 25 andlower layer 27. Each layer may be formed of a semiconductor material. Inan exemplary embodiment, upper layer 23 and lower layer 27 may be formedof the same material with the same bandgap and middle layer 25 may beformed of a different material with a different bandgap thereby formingtwo interfaces 24 and 26, each of which may form a hetero-pn junctionand therefore a quantum well. According to this exemplary embodiment,upper and lower layers 23 and 27 may be formed of an n-type material andmiddle layer 23 formed of a p-type material, or vice versa.

FIGS. 3A-3C illustrate an electron quantum well formed in an exemplarybi-layer floating gate formed of n-Si and p-SiGe. FIG. 3A shows separatebi-layer band diagrams of n-Si and p-Si_(0.5)Ge_(0.5) prior tohetero-junction formation. The n-Si layer has a bandgap of 1.12 electronvolts and p-Si_(0.5)Ge_(0.5) a bandgap of 0.94 electron volts. The righthand side of FIG. 3A also shows a thick bi-layer hetero-junction withcharge neutral region 40 and with aligned Fermi levels E_(F). FIG. 3Bshows a thin and fully depleted bi-layer hetero-junction includingregion 41. The offset of the conduction band between the two materialsin the case when each of the layers are amorphous or polycrystalline,results in electrons accumulated i.e. trapped in the quantum well asshown in FIG. 3C. The depletion layer at the n-Si side having a positivecharge serves as a higher barrier and greater distance for trappedelectrons tunneling toward the n-Si side of the hetero-junction.

FIGS. 4A-4C show hole quantum well formation in an exemplary embodimentin which the floating gate is a bi-layer formed of p-Si and n-SiGe. FIG.4A shows separate bi-layer band diagrams before hereto-junctionformation and the right hand side of FIG. 4A also shows a thick bi-layerhereto-junction with a charge neutral region 44. FIG. 4B shows thin andfully depleted bi-layer hereto-junction 45; and FIG. 4C shows holesaccumulated or trapped in the quantum well. In FIG. 4C, the depletionlayer at the p-Si side serves as a higher barrier and greater distancefor trapped holes tunneling toward the p-Si side.

In other exemplary embodiments, the exemplary Si/SiGe may be replaced byany combination of wide bandgap and narrower bandgap materials, forexample SiC as the wider bandgap material and Ge as the narrower bandgapmaterial. In an exemplary embodiment, the bandgaps of the two adjacentlayers may differ by at least 0.5 eV. The materials may be amorphous,nanocrystalline, or nanoamorphous. In one embodiment, the multi-layerstructure may be a bi-level structure and in various embodiments thebi-layer structure, i.e., semiconductor layers 5 and 7, may be Si/SiGe,Si/SiC, III-IV compound structures such as AlGaAs/GaAs, II-VI compoundstructures such as ZnSe/ZnTe or III-V/II-VI compound structures such asZnSe/GaAs but other multi-layer structures may be used as the floatinggate in other exemplary embodiments.

FIG. 5A shows an exemplary transistor 1 formed over substrate 13 andincluding source/drain regions 51. Stored charge 53 can be seen atinterface 17. Stored charge 53 may be electrons or holes. In theillustrated embodiment and to describe the operation of one exemplaryflash cell, an electron quantum well is formed at interface 17 andtherefore stored charge 53 represents electrons. In the exemplaryembodiment, the flash cell may be an n-type cell and thereforesource/drain regions 51 are n+ materials. The hetero-pn junction formedat interface 17 stores stored charge 53. In this exemplary embodiment,semiconductor layer 5 may be n-Si and semiconductor layer 7 may bep-SiGe with different bandgaps. FIG. 5B shows the device of FIG. 1 inread operation with a Vcc voltage of +0.5 volts applied to control gate15 and source/drain 51 producing current 63 through channel 4. FIG. 5Cshows the device in program operation with a voltage of 5-10 voltsapplied at contact 59 to control gate 15. In other exemplaryembodiments, a program voltage of no greater than 8 volts may be used.FIG. 5C illustrates electrons 61 tunneling toward the quantum wellformed at interface 17 where they will be stored. FIG. 5D shows thedevice in erase operation and with a negative voltage of (−5)-(−10)volts applied to control gate 15 thereby causing electrons 61 to beerased or removed from floating gate 3. The charge carriers, in thiscase electrons 61, tunnel through tunnel-oxide 9 by either F-N tunnelingwhen tunnel-oxide includes a thickness greater than 70 angstroms ordirect tunneling when tunnel-oxide 9 has a lesser thickness. In otherexemplary embodiments, an erase voltage of no greater than 8 volts maybe used. It can be understood that the same but opposite principlesapply when a hole quantum well is utilized.

FIG. 6 is a cross-sectional view showing a fin-FET that includes themulti-layer floating gate of the invention. The aforedescribedprinciples apply similarly to the structure shown in FIG. 6 whichincludes semiconductor fin 73 formed over substrate 71 which may be asemiconductor or SOI substrate. The fin-FET structure includestunnel-oxide 75, upper dielectric 85 and bi-level floating gate 77 whichincludes semiconductor layer 79, semiconductor layer 81 and interface 83formed between the two semiconductor layers. FIG. 6 also includescontrol gate 87. The fin-FET shown in FIG. 6 may be an n-type device,i.e., an n-type channel formed along surface 89 of fin 73, or a p-typefin-FET, and the quantum well may be a hole quantum well or electronquantum well.

The preceding merely illustrates the principles of the invention. Itwill thus be appreciated that those skilled in the art will be able todevise various arrangements which, although not explicitly described orshown herein, embody the principles of the invention and are includedwithin its spirit and scope. Furthermore, all examples and conditionallanguage recited herein are principally intended expressly to be onlyfor pedagogical purposes and to aid the reader in understanding theprinciples of the invention and the concepts contributed by theinventors to furthering the art, and are to be construed as beingwithout limitation to such specifically recited examples and conditions.Moreover, all statements herein reciting principles, aspects, andembodiments of the invention, as well as specific examples thereof, areintended to encompass both structural and functional equivalentsthereof. Additionally, it is intended that such equivalents include bothcurrently known equivalents and equivalents developed in the future,i.e., any elements developed that perform the same function, regardlessof structure.

This description of the exemplary embodiments is intended to be read inconnection with the figures of the accompanying drawing, which are to beconsidered part of the entire written description. In the description,relative terms such as “lower,” “upper,” “horizontal,” “vertical,”,“above,” “below,” “up,” “down,” “top” and “bottom” as well asderivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,”etc.) should be construed to refer to the orientation as then describedor as shown in the drawing under discussion. These relative terms arefor convenience of description and do not require that the apparatus beconstructed or operated in a particular orientation.

Although the invention has been described in terms of exemplaryembodiments, it is not limited thereto. Rather, the appended claimsshould be construed broadly, to include other variants and embodimentsof the invention, which may be made by those skilled in the art withoutdeparting from the scope and range of equivalents of the invention.

1. A floating gate transistor comprising: a lower tunnel-oxide formedover a substrate; an upper dielectric formed over said tunnel-oxide; acontrol gate formed over said upper dielectric; a semiconductor findisposed directly on said substrate and wherein said lower tunnel-oxideis a layer that extends along said substrate and conterminously oversides and top of said semiconductor fin and a channel of said transistoris formed within said semiconductor fin; and a p-n junction formedbetween said tunnel-oxide and said upper dielectric, wherein said p-njunction is a heterojunction formed between two layers of semiconductormaterial having different bandgaps.
 2. The floating gate transistor asin claim 1, wherein said p-n junction comprises a quantum well.
 3. Thefloating gate transistor as in claim 1, wherein said different bandgapsdiffer by at least 0.05 ev.
 4. The floating gate transistor as in claim1, wherein said two layers of semiconductor material comprise a layer ofSiGe and a layer of Si.
 5. The floating gate transistor as in claim 1,wherein said two layers of semiconductor material comprise a first layerformed of III-V material and a second layer formed of II-VI material. 6.The floating gate transistor as in claim 1, wherein said two layers ofsemiconductor material comprise a layer of p-Si and a layer of n-SiGe.7. The floating gate transistor as in claim 1, wherein said lowertunnel-oxide includes a thickness of less than 90 angstroms and saidupper dielectric includes a thickness of less than 90 angstroms.
 8. Thefloating gate transistor as in claim 1, wherein said floating gatetransistor is erasable using a voltage no greater than 8 volts.
 9. Thefloating gate transistor as in claim 1, wherein said floating gatetransistor is programmable using a voltage no greater than 8 volts. 10.The floating gate transistor as in claim 1, wherein said floating gatetransistor is an NMOS transistor and mobile carriers stored at said p-njunction comprise electrons.
 11. The floating gate transistor as inclaim 1, wherein said floating gate transistor is an NMOS transistor andmobile carriers stored at said p-n junction comprise holes.
 12. Thefloating gate transistor as in claim 1, wherein said floating gatetransistor comprises a PMOS transistor.
 13. A floating gate transistorcomprising: a lower tunnel-oxide formed over a substrate; an upperdielectric formed over said tunnel-oxide; a control gate formed oversaid upper dielectric; and a p-n junction formed between saidtunnel-oxide and said upper dielectric, wherein said p-n junction is aheterojunction formed between two layers of semiconductor materialhaving different bandgaps, wherein said two layers of semiconductormaterial comprise a layer of n-Si and a layer of p-SiGe and said p-njunction comprises an electron quantum well.
 14. A semiconductor flashmemory device comprising: a lower tunnel-oxide formed over a substrate;an upper dielectric formed over said tunnel-oxide; a control gate formedover said upper dielectric; a quantum well formed at a p-n junctiondisposed between said tunnel-oxide and said upper dielectric; asemiconductor fin disposed directly on said substrate and wherein saidlower tunnel-oxide is a layer that extends along said substrate andconterminously over sides and top of said semiconductor fin, wherein achannel of a transistor is formed within said semiconductor fin; andcharge stored in said quantum well, wherein said p-n junction is aheterojunction formed between two layers of semiconductor material, saidtwo layers of semiconductor material comprising an n-type layer adjacenta p-type layer and including respective bandgaps that differ by at least0.05 eV.
 15. A floating gate transistor comprising: a lower tunnel-oxideformed over a substrate; an upper dielectric formed over saidtunnel-oxide; a control gate formed over said upper dielectric; and ap-n junction and a further p-n junction formed between said tunnel-oxideand said upper dielectric, wherein each of said p-n junction and saidfurther p-n junction is a heterojunction formed between two layers ofsemiconductor material having different bandgaps, said p-n junction andsaid further p-n junction created by three layers formed between saidlower tunnel-oxide and said upper dielectric, said three layersincluding a middle semiconductor layer with a first bandgap interposedbetween an upper semiconductor layer and a lower semiconductor layereach formed of a material having a different bandgap than said middlesemiconductor layer.